Integrated circuit technologies have continually advanced producing chips that perform more logic operations per unit area and at higher operating speeds. The increased capability of integrated circuits has also created a need for more accurate control of the relationship of various clock or control signals. For example, it may be required in a high speed environment that a second clock signal is delayed a certain amount relative to a first clock signal so that data gated by the first clock signal is in an appropriate state upon the triggering edge of the second clock signal. It may also be required, for example, in the case of asynchronous RAM and two phase latch based design, that one control signal transitions from a given state and returns to that state, while a related control signal does not transition. This relationship is sometimes referred to as "non-overlapping."
One prior art attempt to delay a second clock signal relative to a first clock signal has been to use a latch (flip-flop) to induce a desired delay. Problems with such an approach include that when you are dealing with a high speed clock or control signal, there is no other high speed signal available to gate signals through the latch.
Another prior art attempt to control one clock signal relative to another includes insertion of an analog delay device between the clock signals. Problems with this approach, however, include that the amount of actual delay induced by an analog delay device is quite variable and further that analog delay devices are not part of conventional (digital-based) integrated circuit design tools. A need thus exists for an efficient, practical manner of providing a predefined relationship between multiple clock or control signals in an integrated circuit environment. This need exists for both overlapping and non-overlapping signals.